fpga_quick_ram_update VS zbasic

Compare fpga_quick_ram_update vs zbasic and see what are their differences.

fpga_quick_ram_update

Quickly update a bitstream with new RAM contents (by tomverbeure)

zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems (by ZipCPU)
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fpga_quick_ram_update zbasic
1 4
13 40
- -
1.8 0.0
almost 3 years ago over 1 year ago
Verilog Verilog
The Unlicense -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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fpga_quick_ram_update

Posts with mentions or reviews of fpga_quick_ram_update. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-07-07.
  • Need help with Objcopy for Verilog Hex File
    3 projects | /r/FPGA | 7 Jul 2021
    There are multiple ways to handle this, but I usually first covert the file to pure binary, and then convert it to hex. You could Google about how to do that, or you could use my own ruby script that does the same: https://github.com/tomverbeure/fpga_quick_ram_update/blob/main/misc/create_mif.rb

zbasic

Posts with mentions or reviews of zbasic. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-01-10.
  • AXI Quad SPI 3.2 Flash programming scripts
    5 projects | /r/FPGA | 10 Jan 2022
    Here's sort of a generic repo you can look at which might give you some ideas.
  • How do you successfully compile a working verilator package on Ubuntu?
    1 project | /r/ZipCPU | 27 Jul 2021
    Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
  • Need help with Objcopy for Verilog Hex File
    3 projects | /r/FPGA | 7 Jul 2021
    As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
  • How can I get Verilator to Prompt for User Input?
    3 projects | /r/FPGA | 19 Apr 2021
    The components found in ZBasic will split the stream into two. The key files you'll want there are dbluartsim.cpp and (again) netuart.cpp. To use dbluart, you'll need three pieces: First, you'll need to call setup() to set the baud rate, then once per clock cycle you'll want to call the operator() method--which is really just a rename for the tick() method.

What are some alternatives?

When comparing fpga_quick_ram_update and zbasic you can also consider the following projects:

dbgbus - A collection of debugging busses developed and presented at zipcpu.com

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

dpll - A collection of phase locked loop (PLL) related projects

openarty - An Open Source configuration of the Arty platform

qspiflash - A set of Wishbone Controlled SPI Flash Controllers

arrowzip - A ZipCPU based demonstration of the MAX1000 FPGA board