firrtl
pymtl3
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| firrtl | pymtl3 | |
|---|---|---|
| 4 | 5 | |
| 694 | 350 | |
| 2.9% | 3.7% | |
| 0.0 | 4.6 | |
| 11 days ago | 6 days ago | |
| Scala | Python | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
firrtl
- Firrtl – Flexible Intermediate Representation for RTL
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FPGA Interchange format to enable interoperable FPGA tooling
Did any project other than Chisel make use of FIRRTL? https://github.com/chipsalliance/firrtl
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Scala project (FIRRTL) failing to build on NixOS
I think the protoc comes from here?
pymtl3
- Firrtl – Flexible Intermediate Representation for RTL
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Why are there only 3 languages for FPGA development?
Also PyMTL, PyRTL, and MyHDL.
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Choice of Python HDL library
PyMTL
- RISC-V reference model in Python
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
What are some alternatives?
python-fpga-interchange - Python interface to FPGA interchange format
myhdl - The MyHDL development repository
dotty - The Scala 3 compiler, also known as Dotty.
PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
patchelf - A small utility to modify the dynamic linker and RPATH of ELF executables
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
chisel - Chisel: A Modern Hardware Design Language
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
netlistsvg - draws an SVG schematic from a JSON netlist
hVHDL_fixed_point - VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
firrtl - Flexible Intermediate Representation for RTL
migen - A Python toolbox for building complex digital hardware