firrtl
netlistsvg
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| firrtl | netlistsvg | |
|---|---|---|
| 4 | 4 | |
| 694 | 585 | |
| 2.9% | - | |
| 0.0 | 3.1 | |
| 7 days ago | 3 months ago | |
| Scala | JavaScript | |
| Apache License 2.0 | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
firrtl
- Firrtl – Flexible Intermediate Representation for RTL
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FPGA Interchange format to enable interoperable FPGA tooling
Did any project other than Chisel make use of FIRRTL? https://github.com/chipsalliance/firrtl
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Scala project (FIRRTL) failing to build on NixOS
I think the protoc comes from here?
netlistsvg
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Generation of "high level" block diagram based on verilog files
Maybe this: https://github.com/nturley/netlistsvg
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Logic Primitive Transformations with Yosys Techmap
Great article. Especially needed since Yosys is very difficult to use.
One tip, maybe. Yosys's Graphviz output is frankly incomprehensible shit, and Graphviz isn't very good at laying out these sorts of graphs. But it also can output the information to JSON with the write_json command which lets you use other better tools, e.g. https://github.com/nturley/netlistsvg
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FPGA Interchange format to enable interoperable FPGA tooling
Soon: there are 15 different formats for passing netlists around.
I have very little hope that any netlist format that comes from Yosys. Not only has it changed a couple times in the last years, but the latest iteration is some JSON-based monstrosity that has to be by far the most inconvenient netlist format ever created (see https://github.com/nturley/netlistsvg/blob/master/test/digit... ) .
- Show HN: Pylectronics – Reproduce digital electronics in Python
What are some alternatives?
python-fpga-interchange - Python interface to FPGA interchange format
beautiful-react-diagrams - 💎 A collection of lightweight React components and hooks to build diagrams with ease 💎
dotty - The Scala 3 compiler, also known as Dotty.
patchelf - A small utility to modify the dynamic linker and RPATH of ELF executables
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
chisel - Chisel: A Modern Hardware Design Language
ideas - Random ideas and interesting ideas for things we hope to eventually do.
firrtl - Flexible Intermediate Representation for RTL
pylectronics - Reproduce digital electronics in Python