firrtl
python-fpga-interchange
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firrtl | python-fpga-interchange | |
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4 | 1 | |
688 | 38 | |
3.1% | - | |
0.0 | 0.0 | |
9 days ago | over 1 year ago | |
Scala | Python | |
Apache License 2.0 | ISC License |
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firrtl
- Firrtl – Flexible Intermediate Representation for RTL
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FPGA Interchange format to enable interoperable FPGA tooling
Did any project other than Chisel make use of FIRRTL? https://github.com/chipsalliance/firrtl
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Scala project (FIRRTL) failing to build on NixOS
I am trying to build an SBT based project called FIRRTL on NixOS in a nix-shell (I've tried with and without --pure). However, the build keeps failing on NixOS, but it successfully builds in a --pure shell on macOS (11.2.1). Since I'm not really a Scala developer (trying to get into chisel for RTL), I have no idea what could be missing from my .nix which is available on macOS by default.
I think the protoc comes from here?
python-fpga-interchange
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FPGA Interchange format to enable interoperable FPGA tooling
Or BLIF or EBLIF (already used by the verilog-to-routing flow). But no, let's invent yet another netlist format.
The fact that all of these existing formats are all named "xxx logic interchange format" should give you an idea what will happen to this new "interchange format".
From what I gather ( https://github.com/SymbiFlow/python-fpga-interchange/blob/ma... ) , the new format is basically the existing Yosys/nextpnr JSON format except dumped as a Cap'n Proto binary file.
I am absolutely not impressed.
I guess the meat here is on the universal device resources format, but this is not cool anyway.
What are some alternatives?
dotty - The Scala 3 compiler, also known as Dotty.
patchelf - A small utility to modify the dynamic linker and RPATH of ELF executables
netlistsvg - draws an SVG schematic from a JSON netlist
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
firrtl - Flexible Intermediate Representation for RTL
chisel - Chisel: A Modern Hardware Design Language
ideas - Random ideas and interesting ideas for things we hope to eventually do.