esp
Vitis-Tutorials
esp | Vitis-Tutorials | |
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1 | 4 | |
301 | 1,070 | |
2.0% | 3.1% | |
7.5 | 9.3 | |
25 days ago | 6 days ago | |
C | C | |
GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
esp
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
What are some alternatives?
ara - The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Vitis-HLS-Introductory-Examples
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
o1heap - Constant-complexity deterministic memory allocator (heap) for hard real-time high-integrity embedded systems. There is very little activity because the project is finished and does not require further changes.
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
litex - Build your hardware, easily!