deepsocflow
clash-ghc
deepsocflow | clash-ghc | |
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1 | 33 | |
36 | 1,376 | |
- | 1.2% | |
9.1 | 9.1 | |
8 days ago | 5 days ago | |
Python | Haskell | |
Apache License 2.0 | BSD 2-clause "Simplified" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
deepsocflow
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Xilinx xsim is BLAZINGLY FAST. Xsim dumping all signals 5x faster than Icarus Verilog dumping no signals!
Here's the testbench. I've written a python script to generate test vectors, generate batch file for xsim, run icarus/xsim and compare output. Feel free to star my project repo, if you like it.
clash-ghc
- Clash: A Functional Hardware Description Language
- Clash (Haskell) for ASIC design
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Building a Networked Key-Value-Store on an FPGA
> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.
As is Clash :) https://clash-lang.org/
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Need project idea
You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/
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5 layered CNN implementation on arduino/FPGAs [P]
I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org
- An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
- Pedagogical Downsides of Haskell
- Ask HN: Choice of HDL for an FPGA Project
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Baud rate 1.5% lower than expected, is this normal?
if you need inspiration there is a full UART core available in clash: https://github.com/clash-lang/clash-compiler/blob/master/clash-cores/src/Clash/Cores/UART.hs
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A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
What are some alternatives?
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
wiringPi - A Haskell binding to the wiringPi library, for using GPIO on the Raspberry Pi.
clash-prelude
mercury-api - Haskell binding to Mercury API for ThingMagic RFID readers
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
amaranth - A modern hardware definition language and toolchain based on Python
verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
hidapi - Haskell HIDAPI bindings
clash-prelude-quickcheck - QuickCheck instances for various types in the CλaSH Prelude
serialport - Cross platform haskell library for using the serial port
retroclash-lib - Library code for upcoming RetroClash book