ddr3-controller
hdl
| ddr3-controller | hdl | |
|---|---|---|
| 3 | 5 | |
| 55 | 1,395 | |
| - | 1.2% | |
| 0.0 | 9.3 | |
| over 1 year ago | 6 days ago | |
| Verilog | Verilog | |
| - | GNU General Public License v3.0 or later |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ddr3-controller
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Best tutorial on DDR protocol
Shameless plug: Take a look at my own design. I also have apaper written about it.
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Does anybody have a working SDRAM DDR2 Controller for Cyclone III FPGA?
If /u/UseDelicious4662 wants to port some code to their device, they could look at my DDR3 controller for Xilinx 7 Series. It's 1400 lines of code, and it's as simple as I could make it. The PHY is as good as done, even for DDR2. The logic part needs some work to be compatible with an older generation of DDR SDRAM, but overall it should be portable enough. Once that adaptation is done, they "only" need to figure out how to instantiate the Altera counterparts of OSERDES, ISERDES, and IDELAY. https://github.com/someone755/ddr3-controller
- A custom DDR3 controller for the Arty S7-50 board
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
control_cpu - FPGA setup with memory and Risc V CPU
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
simple_ddr_ctrl - A (very) simple DDR3 controller for FPGAs
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
uhd - The USRP™ Hardware Driver Repository
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
USB_C_Industrial_Camera_FPGA_USB3 - Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.