corundum
xfcp
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corundum | xfcp | |
---|---|---|
28 | 5 | |
1,460 | 51 | |
3.7% | - | |
9.4 | 0.0 | |
4 months ago | 12 months ago | |
Verilog | Verilog | |
GNU General Public License v3.0 or later | MIT License |
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corundum
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Open sourceCorundum – FPGA-based NIC and platform for in-network compute
- TCP checksum computation
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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xilinx versal gty testbench/data gen?
Well, I did build this: https://github.com/corundum/corundum
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FPGA for finance industry
I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .
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Computer Networking Nerd and EE Student Looking to build a Baremetal Network Driver on top of baremetal kernel? Is this possible and if so, I'd like some guidance!
I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.
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Device Drivers for Transceiver Questions (Specifically, PCIe)
If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum
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shift/concatenate in v/sv
I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.
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Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
xfcp
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Ethernet PC-FPGA interface
This is exactly what I created https://github.com/alexforencich/xfcp for - Ethernet and serial to multiple internal components, with the ability to enumerate said components.
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Options for control and configuration of FPGA from PC
This is basically what I made XFCP for: https://github.com/alexforencich/xfcp
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .
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FPGA development live stream: FPGA board bring-up and testing of high-speed serializers
I'll use my XFCP project to interface with the FPGA from Python via a USB serial chip. This provides access to the I2C bus on the board, for configuring the PLL chips and interfacing with the QSFP28 optical transceivers. Additionally, it connects to the dynamic reconfiguration ports (DRP) on the GTY transceivers, and I'll use that for performing BER measurements at 25 Gbps through a handful of QSFP28 cables and optical modules. It looks like I might also have to do some fine-tuning of some of the analog parameters on the transceivers (namely pre-emphasis).
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FPGA development live stream: FPGA board bring-up and testing
I recently acquired a pair of rather large FPGA boards that have a bunch of high-speed IO. I figure it might be interesting to show the process for bringing them up in terms of the reference clock generation and distribution components on the board for the high-speed serializers, as well as performing some simple sanity checks (BER testing) on all of the interfaces to make sure everything is operational. I'll use my XFCP project to interface with the FPGA from Python for configuring the clocking components over I2C and for performing the BER measurements on the GTY transceivers via DRP.
What are some alternatives?
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SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
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litex - Build your hardware, easily!
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SpinalHDL - Scala based HDL
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satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images