control_cpu
FPGA setup with memory and Risc V CPU (by CompuSAR)
ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs (by someone755)
| control_cpu | ddr3-controller | |
|---|---|---|
| 2 | 3 | |
| 3 | 55 | |
| - | - | |
| 6.3 | 0.0 | |
| 26 days ago | over 1 year ago | |
| SystemVerilog | Verilog | |
| GNU General Public License v3.0 only | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
control_cpu
Posts with mentions or reviews of control_cpu.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-11.
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Best tutorial on DDR protocol
I ended up using both, though you'd be excused for not seeing that from my design. This design was meant to be absolutely minimal in size, and one of the ways it does this is by assuming there is a CPU involved. So a lot of the DDR initialization is done in software (you can find it here). All register assignment and mode switching is done from there, as well as entering and leaving the write leveling mode and the whole read calibration logic.
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How can "worst negative slack" become _worse_ when I *lower* the clock?
In case anyone is interested, the design is at https://github.com/CompuSAR/control_cpu. You'll need to fetch the submodules (git submodule update --init) and erase the mcp file from the project for Vivado to generate it. The code as is in the repo is at 100MHz, which passes timing. Raising it to 120MHz or to 115MHz shows the problem. The clock speed register is set from a localparam at top.sv line 51.
ddr3-controller
Posts with mentions or reviews of ddr3-controller.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-11.
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Best tutorial on DDR protocol
Shameless plug: Take a look at my own design. I also have apaper written about it.
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Does anybody have a working SDRAM DDR2 Controller for Cyclone III FPGA?
If /u/UseDelicious4662 wants to port some code to their device, they could look at my DDR3 controller for Xilinx 7 Series. It's 1400 lines of code, and it's as simple as I could make it. The PHY is as good as done, even for DDR2. The logic part needs some work to be compatible with an older generation of DDR SDRAM, but overall it should be portable enough. Once that adaptation is done, they "only" need to figure out how to instantiate the Altera counterparts of OSERDES, ISERDES, and IDELAY. https://github.com/someone755/ddr3-controller
- A custom DDR3 controller for the Arty S7-50 board
What are some alternatives?
When comparing control_cpu and ddr3-controller you can also consider the following projects:
simple_ddr_ctrl - A (very) simple DDR3 controller for FPGAs