How can "worst negative slack" become _worse_ when I *lower* the clock?

• control_cpu

  2 3 6.5 SystemVerilog

  FPGA setup with memory and Risc V CPU

  

In case anyone is interested, the design is at https://github.com/CompuSAR/control_cpu. You'll need to fetch the submodules (git submodule update --init) and erase the mcp file from the project for Vivado to generate it. The code as is in the repo is at 100MHz, which passes timing. Raising it to 120MHz or to 115MHz shows the problem. The clock speed register is set from a localparam at top.sv line 51.

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