cocotb VS iverilog

The use of cocotb and pyuvm for verification

For FPGA/HDL work, there's cocotb

At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.

On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.

I know it might be difficult without much context, but this makefile is called by a top level makefile. very confused if lines 35-74 do anything. They seem to be a mix of real makefile syntax and just straight up comments. what do these lines do?

Learn more about this here: https://www.cocotb.org/

Also consider cocotb, this thread has some compelling arguments. I'd say as a student, learning industry tools isn't necessarily the best thing you could spend your time on. Getting fast at design AND verification, where you can maintain flow state and run better microexperiments means you will understand more, faster.

Have you tried looking at the mixed language example?

Also, Icarus says that they do not support assertions in their full-generality either:

The toolchains come with their own simulators, but there are also open source ones you can use. For Verilog you have ICARUS Verilog and Verilator. For VHDL there is GHDL.

This is not, in general, true. While iverilog may support some SV features, it is far from complete and does not support some very common use cases. For example, interfaces.

However, I find that it's always read-before-write in Icarus Verilog. Is my tool wrong? Is the book wrong? Is this situation actually ambiguous?

I have no intention to run it on real FPGA ever, Icarus Verilog simulator suits me well enough.

As the idea was to make it more realistic, I started by making (hopefully accurate representation of) 74-series logic chips in Verilog. Then wired them into higher level modules, and merged those into complete CPU. Runs quite good in Icarus Verilog.

I'd suggest starting with simulation using Icarus Verilog or Verilator. And gtkwave to display simulation output.

We'll specifically be using Icarus Verilog.

In the open-source world, learning UVM isn't practical. There just isn't a simulator that can run it. However, if you use something like PyUVM with CocoTB, along with verilator or Icarus as an RTL simulator you code start writing test benches around some simple verilog components.