iverilog VS veridian

Also, Icarus says that they do not support assertions in their full-generality either:

The toolchains come with their own simulators, but there are also open source ones you can use. For Verilog you have ICARUS Verilog and Verilator. For VHDL there is GHDL.

This is not, in general, true. While iverilog may support some SV features, it is far from complete and does not support some very common use cases. For example, interfaces.

However, I find that it's always read-before-write in Icarus Verilog. Is my tool wrong? Is the book wrong? Is this situation actually ambiguous?

I have no intention to run it on real FPGA ever, Icarus Verilog simulator suits me well enough.

As the idea was to make it more realistic, I started by making (hopefully accurate representation of) 74-series logic chips in Verilog. Then wired them into higher level modules, and merged those into complete CPU. Runs quite good in Icarus Verilog.

I'd suggest starting with simulation using Icarus Verilog or Verilator. And gtkwave to display simulation output.

We'll specifically be using Icarus Verilog.

In the open-source world, learning UVM isn't practical. There just isn't a simulator that can run it. However, if you use something like PyUVM with CocoTB, along with verilator or Icarus as an RTL simulator you code start writing test benches around some simple verilog components.

SystemVerilog

Neovim's native LSP support with Slang and/or Verible + https://github.com/vivekmalneedi/veridian