Surelog
verible
| Surelog | verible | |
|---|---|---|
| 1 | 6 | |
| 330 | 1,197 | |
| 2.7% | 1.8% | |
| 9.4 | 9.3 | |
| 2 months ago | 11 days ago | |
| C++ | C++ | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Surelog
verible
-
How to instance module with auto-completion for verilog in neovim?
I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?
-
Verilog LRM syntax rules
BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.
-
Reliable Verilog dependency analysis
You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.
-
svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
-
Tools like Scitools Understand but support Verilog
https://github.com/chipsalliance/verible (may not do actual syntax checking)
-
Forking rustfmt for another language
You might be interested in this though.
What are some alternatives?
slang - SystemVerilog compiler and language services
sleighcraft - sleigh craft!
svls - SystemVerilog language server
naja-verilog - A standalone structural (gate-level) verilog parser
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
veridian - A SystemVerilog Language Server
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
tree-sitter-html - HTML grammar for Tree-sitter
quick-lint-js - quick-lint-js finds bugs in JavaScript programs
iverilog - Icarus Verilog