Surelog
naja-verilog
Surelog | naja-verilog | |
---|---|---|
1 | 2 | |
330 | 21 | |
2.7% | - | |
9.4 | 7.6 | |
2 months ago | about 1 month ago | |
C++ | C++ | |
Apache License 2.0 | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Surelog
naja-verilog
-
Naja-Verilog: stand-alone structural (gate-level) parser
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
- Show HN: Naja-Verilog – Structural Verilog Parser
What are some alternatives?
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Degate - A modern and open-source cross-platform software for chips reverse engineering.
slang - SystemVerilog compiler and language services
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
sleighcraft - sleigh craft!
verilator - Verilator open-source SystemVerilog simulator and lint system
naja - Structural Netlist API (and more) for EDA post synthesis flow development
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.
quick-lint-js - quick-lint-js finds bugs in JavaScript programs
Diagon - Interactive ASCII art diagram generators. :star2: