caravel_fulgor_opamp VS openlane

Compare caravel_fulgor_opamp vs openlane and see what are their differences.

caravel_fulgor_opamp

Test Chip General Purpose OpAmp using Skywater SKY130 PDK (by diegohernando)

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. (by efabless)
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caravel_fulgor_opamp openlane
1 12
15 1,118
- 3.6%
10.0 8.8
almost 3 years ago 5 days ago
Verilog Python
Apache License 2.0 Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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caravel_fulgor_opamp

Posts with mentions or reviews of caravel_fulgor_opamp. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-12-14.

openlane

Posts with mentions or reviews of openlane. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-15.
  • [D][P] Represent Analog Circuits as Graphs
    3 projects | /r/MachineLearning | 15 Apr 2023
    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
  • VLSI Tools
    6 projects | /r/chipdesign | 14 Dec 2022
    OpenLane
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
  • Kickstarting IC design
    2 projects | /r/chipdesign | 3 Dec 2021
    And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
  • How are modern processors and their architecture designed?
    4 projects | /r/ECE | 28 Sep 2021
    For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
  • Project Ideas for Uni
    2 projects | /r/FPGA | 23 Aug 2021
    Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.

What are some alternatives?

When comparing caravel_fulgor_opamp and openlane you can also consider the following projects:

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

rocket-chip - Rocket Chip Generator

NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上

riscv - RISC-V CPU Core (RV32IM)

opentitan - OpenTitan: Open source silicon root of trust

sv2v - SystemVerilog to Verilog conversion

zerosoc - Demo SoC for SiliconCompiler.

Verilog.jl - Verilog for Julia

Slime-Simulation

OpenROAD-flow-scripts - OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/