captouch VS spi-fpga

Compare captouch vs spi-fpga and see what are their differences.

captouch

👇 Add capacitive touch buttons to any FPGA! (by stnolting)
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captouch spi-fpga
2 2
97 157
- -
0.0 0.0
about 2 years ago about 3 years ago
VHDL VHDL
BSD 3-clause "New" or "Revised" License MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

captouch

Posts with mentions or reviews of captouch. We have used some of these posts to build our list of alternatives and similar projects.

spi-fpga

Posts with mentions or reviews of spi-fpga. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing captouch and spi-fpga you can also consider the following projects:

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

w11 - PDP-11/70 CPU core and SoC

wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

fpu - IEEE 754 floating point library in system-verilog and vhdl

sdram-fpga - A FPGA core for a simple SDRAM controller.