autofpga VS VexRiscv

I use AutoFPGA for connecting my top level components together. It handles bus composition and address assignment for me, while also creating linker, C header and Verilator simulation files for the project. Once a project is set up, reconfiguration is as easy as adding a file to the command line to add a component, or removing a file from the command line to remove a component. Make handles the rest.

I use AutoFPGA for all my bus connections. A single @$(SLAVE.PORTLIST) or @$(SLAVE.ANSPORTLIST) automatically expands into the connections required when instantiating a module. It'll also instantiate the crossbar for you as well.

Yes, I have posted an open source AXI interconnect. Unlike Xilinx's interconnect, mine doesn't automatically bridge between one bus width or clock and another, although some bridges exist in the same repository. Bridges exist, for example, for crossing clock domains, going from AXI3 to AXI4, from AXI4 to AXI4-lite, from AXI4 to a smaller AXI4-lite, and from AXI4-lite to a wider width. It's been enough to keep me from needing my own AXI4 interconnect, although AXI can be a real pain to wire up. As a result, I tend to use AutoFPGA for that purpose.

Now, whether or not AutoFPGA fits the bill for anyone--that's an entirely different question. I suspect the answer is, "No", but that's really a different conversation for a different time/thread. One of the things it can do is compose an AXI bus from multiple master and slave configurations--all using user controlled and very version controllable configuration files. The big problem it has (currently) is the lack of a strong verification suite. That's probably going to hit the top of my to-do list soon enough.

An SoC composer? You'll need something that takes multiple bus components and stitches them together. I've used AutoFPGA extensively for this purpose, and continue to do so today. It's biggest problem? I haven't put a lot of energy into marketing it, so the documentation is more lacking than I would like. Still, it's worked quite well for me and my intermediate tutorial (work in progress) provides some discussion of how to work with it.

AutoFPGA can do simple bus line pattern substitution. For example, these two configuration lines then expand to these 65 lines.

There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.

I generated my own solution to this problem, a solution which I called AutoFPGA. It's not IP-XACT. It configures a design based upon a bus with (potentially) multiple masters and slaves. Configuration files are designed on a per-unit basis, with the intention that a slave (or master) configuration file could be removed to remove that portion of the design from the whole.

If you wish to build a SOC design, you'll need some approach to assembling the bus together. There will be a lot of wires to connect, and a lot of logic to build just to get you off the ground. You'll find several SOC based building tools out there to use. I've built my own, AutoFPGA, which I use for assembling peripherals around a CPU based design. You might find an open source crossbar interconnect to be quite valuable as well. I've built crossbars for AXI, AXI-lite, and Wishbone (pipeline). I know there's a good Wishbone classic crossbar out there as well, I just don't have the link at my fingertips. (Good? It'll slow down your overall clock speed, while yielding poorer performance compared to Wishbone pipeline--but that's just the reality of working with Wishbone classic.)

With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

I don't get what's going on with licensing and device support. I'm missing something here perhaps, but we use Cyclone 10 GX onwards and Quartus Pro so I don't have enough context maybe. Have you considered swapping your Nios ii to a VexRISCV as a side note? At ~1 Dhrystone MIPS/MHz it's roughly double that of the Nios V, for very few resources. All open source too. None of the migration documentation support though, so I can't judge how hard it would be.

If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.

Something like https://github.com/SpinalHDL/VexRiscv will take far fewer

A CPU built around the Gentoo philosophy would look like https://github.com/SpinalHDL/VexRiscv ;). Don't want an MMU? Fine. Need a larger RAM interface? You got it. Barrel ALU for DSP? Sure.

Interpreted languages work by consolidating all of the optimization effort in the interpreter. This is similar to how CPUs work now, instead of extremely specific optimizations that are hard to create distributed among all code we use very general optimizations that push the limits of mathematics that is centralized in a CPU.

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Itanium had a lot of contemporary issues that made it not work. I would certainly blame Intel's business practices and reputation for a large part of it. There are likely niches for such processors. The VLIW is useful for DSP or graphics. Indeed, the only extant VLIW (that I know of) processor is the Russian Elbrus. I think the VLIW is only included to let them reuse a lot of the core logic of the CPU to drive a DSP engine, useful for radar and scientific simulation, though the sci sim would probably use commercial hardware which would be faster.

It works on GPUs because they're doing DSP, basically. We could have weirder topologies for GPUs however, like a massive string of ALUs driven off an embedded core, so you try to kachunk all your data in a single clock domain after configuring the ALU string.

4) https://github.com/SpinalHDL/VexRiscv

I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.

I'd recommend giving vexriscv a look. It'll handily fit on your FPGA, leaving plants of room for I2C, VGA output, and whatever multiplication you end up wanting to do. It's very easy to get set up, and their example "briey" SOC even has VGA output already, but not hardware I2C (though you could easily bitbang it with the core). Adding in I2C via a "plugin" should be trivial.