apio
prince
| apio | prince | |
|---|---|---|
| 3 | 1 | |
| 754 | 7 | |
| 1.7% | - | |
| 9.7 | 3.5 | |
| 5 days ago | 4 months ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 only | BSD 2-clause "Simplified" License |
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apio
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Looking for help getting started with TinyFPGA
apio is a python package you drive from the command line. I didn't know somebody had done an integration with Atom. I've installed and used apio on my phone. I wouldn't really recommend doing that, but it shows what's possible.
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Learning Verilog and FPGA
I've had good experiences using Upduino 3.0 and 3.1 [0] with the IceStorm tools via apio [1]. I wrote a blog post [2] with some info on getting things set up via Linux. All you need is the Upduino board, which interfaces to your host system via USB (so no special programmer is needed).
[0] https://tinyvision.ai/products/upduino-v3-1
[1] https://github.com/FPGAwars/apio
[2] https://daveho.github.io/2021/02/07/upduino3-getting-started...
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FPGA dev board that's cheap, simple and supported by OSS toolchain
if you're more comfortable with the CLI, you should take a look at the apio project (https://github.com/FPGAwars/apio). It neatly bundles all the required tools. Regarding HDLs, I'm still learning so can't offer any good advice on that.
prince
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Learning Verilog and FPGA
I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS on a statement has been updated.
IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.
https://github.com/secworks/prince/blob/master/src/rtl/princ...
The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
What are some alternatives?
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
UPduino-v3.0 - UPduino 3.0: new 4 layer layout, various other improvements
6502-exp - 6502 Computer FPGA Peripherals
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
vhdl-tutorial
icestudio - :snowflake: Visual editor for open FPGA boards
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
edalize - An abstraction library for interfacing EDA tools
fomu-toolchain - A collection of tools for developing for Fomu
nmigen-tutorial - A tutorial for using nmigen