Prince Alternatives
Similar projects and alternatives to prince
-
f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
-
WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
-
InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
prince reviews and mentions
-
Learning Verilog and FPGA
I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS on a statement has been updated.
IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.
https://github.com/secworks/prince/blob/master/src/rtl/princ...
The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
Stats
secworks/prince is an open source project licensed under BSD 2-clause "Simplified" License which is an OSI approved license.
The primary programming language of prince is Verilog.
Popular Comparisons
Sponsored