prince
6502-exp
prince | 6502-exp | |
---|---|---|
1 | 1 | |
7 | 0 | |
- | - | |
3.5 | 10.0 | |
4 months ago | about 3 years ago | |
Verilog | Assembly | |
BSD 2-clause "Simplified" License | - |
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prince
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Learning Verilog and FPGA
I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS on a statement has been updated.
IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.
https://github.com/secworks/prince/blob/master/src/rtl/princ...
The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
6502-exp
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Learning Verilog and FPGA
Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chisel project. Therefore it is already supported by practically all vendors and simulators.
I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...
What are some alternatives?
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
apio - :seedling: Open source ecosystem for open FPGA boards
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
vhdl-tutorial
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.