SpinalHDL
corundum
SpinalHDL | corundum | |
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8 | 28 | |
1,523 | 1,478 | |
2.0% | 2.7% | |
9.8 | 9.0 | |
6 days ago | 6 days ago | |
Scala | Verilog | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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SpinalHDL
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1800-2023 – IEEE Standard for SystemVerilog
I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.
I really like what Zig and C++ are doing with `const`.
https://ikrima.dev/dev-notes/zig/zig-metaprogramming/
Have you looked at Spinal?
https://github.com/SpinalHDL/SpinalHDL
https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Simple skid buffer implementation
I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.
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Why are there only 3 languages for FPGA development?
Don’t forget SpinalHDL that was forked off of Chisel 2 I believe. These DSLs really leveraged the software features of Scala to help build generalised/modular systems. And are generally a quality of life improvement in the language features available.
- SpinalHDL – A high level hardware description language based on Scala
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
- Chisel/Firrtl Hardware Compiler Framework
corundum
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Open sourceCorundum – FPGA-based NIC and platform for in-network compute
- TCP checksum computation
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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xilinx versal gty testbench/data gen?
Well, I did build this: https://github.com/corundum/corundum
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FPGA for finance industry
I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .
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Computer Networking Nerd and EE Student Looking to build a Baremetal Network Driver on top of baremetal kernel? Is this possible and if so, I'd like some guidance!
I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.
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Device Drivers for Transceiver Questions (Specifically, PCIe)
If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum
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shift/concatenate in v/sv
I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.
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Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
What are some alternatives?
chisel - Chisel: A Modern Hardware Design Language
verilog-ethernet - Verilog Ethernet components for FPGA implementation
amaranth - A modern hardware definition language and toolchain based on Python
rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.
litex - Build your hardware, easily!
NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.
chiselverify - A dynamic verification library for Chisel.
litepcie - Small footprint and configurable PCIe core
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
circt - Circuit IR Compilers and Tools
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA