SVA-AXI4-FVIP
YosysHQ SVA AXI Properties (by YosysHQ-GmbH)
AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components (by OSVVM)
| SVA-AXI4-FVIP | AXI4 | |
|---|---|---|
| 3 | 4 | |
| 23 | 103 | |
| - | 6.8% | |
| 10.0 | 7.6 | |
| about 1 year ago | 23 days ago | |
| SystemVerilog | VHDL | |
| ISC License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
SVA-AXI4-FVIP
Posts with mentions or reviews of SVA-AXI4-FVIP.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-02.
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Reference of verification IPs
sby file
AXI4
Posts with mentions or reviews of AXI4.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-02.
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I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
- Reference of verification IPs
- Verilog Text Book Recommendations?
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Entity Input Ports
If you are looking for an AXI Subordinate (new AXI spec names) Memory, you may wish to look at the one from OSVVM (it is free open source (FOSS)). You will find it at: https://github.com/OSVVM/AXI4/blob/master/Axi4/src/Axi4Memory.vhd
What are some alternatives?
When comparing SVA-AXI4-FVIP and AXI4 you can also consider the following projects:
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
wb2axip - Bus bridges and other odds and ends
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
blob
rust_hdl
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
vc_axi