PipelineC
hVHDL_floating_point
| PipelineC | hVHDL_floating_point | |
|---|---|---|
| 46 | 3 | |
| 548 | 13 | |
| - | - | |
| 9.5 | 8.2 | |
| 10 days ago | about 1 month ago | |
| Python | VHDL | |
| GNU General Public License v3.0 only | MIT License |
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PipelineC
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PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
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What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
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What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
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Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software
hVHDL_floating_point
- Generating pipeline stages automatically?
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Choice of Python HDL library
The file has 86 lines, but this functionality could be implemented with just 10 lines of code by using a procedure call to create_first_order_filter which can is defined here https://github.com/hVHDL/hVHDL_floating_point/blob/main/float_first_order_filter/float_first_order_filter_pkg.vhd
- How would you go about writing a pipeline with backpressure? - VHDL
What are some alternatives?
pygears - HW Design: A Functional Approach
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
pycparser - :snake: Complete C99 parser in pure Python
migen - A Python toolbox for building complex digital hardware
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
hVHDL_fixed_point - VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
hls4ml - Machine learning on FPGAs using HLS
myhdl - The MyHDL development repository
antikernel - The Antikernel operating system project
magma - magma circuits