a2o
kianRiscV
| a2o | kianRiscV | |
|---|---|---|
| 2 | 1 | |
| 35 | 487 | |
| - | - | |
| 1.4 | 7.8 | |
| 3 months ago | 4 days ago | |
| Verilog | AGS Script | |
| GNU General Public License v3.0 or later | ISC License |
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a2o
-
Arm wants to charge dramatically more for chip licenses
Yes, there are open core IPs for POWER:
- https://github.com/OpenPOWERFoundation/a2i
- https://github.com/OpenPOWERFoundation/a2o
- https://github.com/antonblanchard/microwatt
- How long until RISC gets adopted for the desktop?
kianRiscV
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Have I discovered a synthesis/routing defect with the Gowin IDE?
I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.
What are some alternatives?
a2i - The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
biriscv - 32-bit Superscalar RISC-V CPU
ice40_power - Power analysis of the ICE40UP5K-SG48 devices
my_hdmi_device - New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
xcat-core - Code repo for xCAT core packages
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
microwatt - A tiny Open POWER ISA softcore written in VHDL 2008
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
s1-ecg-demo - An all-in-one kit to deploy and test ECG algorithms with ease. Based on the AD8233 and S1 Module, this open source board is a great for new products, as well as research and teaching.
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv - RISC-V CPU Core (RV32IM)