ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32 (by FelipeFFerreira)
fpga_riscv_cpu
fpga verilog risc-v rv32i cpu (by nobotro)
| ITA-CORES | fpga_riscv_cpu | |
|---|---|---|
| 1 | 1 | |
| 34 | 8 | |
| - | - | |
| 8.7 | 1.1 | |
| 6 months ago | about 1 year ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ITA-CORES
Posts with mentions or reviews of ITA-CORES.
We have used some of these posts to build our list of alternatives
and similar projects.
fpga_riscv_cpu
Posts with mentions or reviews of fpga_riscv_cpu.
We have used some of these posts to build our list of alternatives
and similar projects.
What are some alternatives?
When comparing ITA-CORES and fpga_riscv_cpu you can also consider the following projects:
RISC-V - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
friscv - RISCV CPU implementation in SystemVerilog
Hazard3 - 3-stage RV32IMACZb* processor with debug