Compliance-Tests
spi-fpga
Compliance-Tests | spi-fpga | |
---|---|---|
1 | 2 | |
25 | 157 | |
- | - | |
4.0 | 0.0 | |
6 days ago | about 3 years ago | |
VHDL | VHDL | |
Apache License 2.0 | MIT License |
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Compliance-Tests
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VHDL Testbench Library Comparison
There is an initiative for feature support here: https://github.com/VHDL/Compliance-Tests/ but is has not been active for over a year. With a compliance test anyone can test their own simulator or simulators they are evaluating. A public comparison is trickier as such benchmarking is typically prohibited by the license.
spi-fpga
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The accelerometer on the CYC1000 FPGA board.
Last year I did experiments with the accelerometer on the CYC1000 FPGA board. The result is the Spirit Level example for my Git repository with SPI controllers. I also started using GHDL in GitHub Actions to automate my simulations. It is an easy-to-use CI for VHDL projects. https://github.com/jakubcabal/spi-fpga
- Does anyone have a Slave Quad SPI in VHDL?
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
w11 - PDP-11/70 CPU core and SoC
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
fpu - IEEE 754 floating point library in system-verilog and vhdl
sdram-fpga - A FPGA core for a simple SDRAM controller.