bsc
clash-ghc
bsc | clash-ghc | |
---|---|---|
8 | 33 | |
880 | 1,375 | |
1.0% | 1.2% | |
8.4 | 9.1 | |
25 days ago | 4 days ago | |
Haskell | Haskell | |
GNU General Public License v3.0 or later | BSD 2-clause "Simplified" License |
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bsc
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
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Is “x' = f(x)” a programming paradigm?
In a previous project we used Haskell that compiled down to Verilog to design hardware. Think along the lines of BlueSpec or Clash. Haskell would force you to spell out the new state as a function of the old state of the system. This would let us do gate-level simulations of the hardware we designed. Coupled with Haskell's penchant for using primes to mean "the new value of", stuff like x' = f x was very common.
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I'm starting a project to make a Rust-like hardware description language and I need your opinions.
You should look at Bluespec, they are doing some interesting stuff.
- Verilog Is Weird
- Bluespec hardware design language and simulation tools
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MyHDL: Using Python as a hardware description and verification language
And I've been involved in a project that's making heavy use of Bluespec: https://github.com/B-Lang-org/bsc/
Same problem though - you have to transpile it down to Verilog to use it in anything beyond a simulation.
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FPGA dev board that's cheap, simple and supported by OSS toolchain
FPGA Thread: Bluespec SystemVerilog is now completely open source, very nice HDL although quite opinionated.
https://github.com/B-Lang-org/bsc
it's Haskell underneath (https://xkcd.com/356/)
clash-ghc
- Clash: A Functional Hardware Description Language
- Clash (Haskell) for ASIC design
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Building a Networked Key-Value-Store on an FPGA
> You'd be better off with a higher-level or more modern HDL that compiles to Verilog/VHDL. "Chisel" is one such.
As is Clash :) https://clash-lang.org/
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Need project idea
You can take a look at https://clash-lang.org/. There is also a book for it. https://gergo.erdi.hu/retroclash/
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5 layered CNN implementation on arduino/FPGAs [P]
I don't know much about FPGAs, but Clash lang compiles to VHDL, and might do the trick: https://clash-lang.org
- An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
- Pedagogical Downsides of Haskell
- Ask HN: Choice of HDL for an FPGA Project
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Baud rate 1.5% lower than expected, is this normal?
if you need inspiration there is a full UART core available in clash: https://github.com/clash-lang/clash-compiler/blob/master/clash-cores/src/Clash/Cores/UART.hs
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A circuit simulator that doesn't look like it was made in 2003
Perhaps peripheral (the original site has been hugged to death).
Both clashlang: https://clash-lang.org/
And Hardcaml: https://github.com/janestreet/hardcaml
have personally fueled my interest in hardware.
Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.
What are some alternatives?
chisel - Chisel: A Modern Hardware Design Language
wiringPi - A Haskell binding to the wiringPi library, for using GPIO on the Raspberry Pi.
UPduino-v3.0 - UPduino 3.0: new 4 layer layout, various other improvements
clash-prelude
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
mercury-api - Haskell binding to Mercury API for ThingMagic RFID readers
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
ICFP2020_Bluespec_Tutorial - Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
rustylog - A Rust-like Hardware Description Language transpiled to Verilog
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
fomu-toolchain - A collection of tools for developing for Fomu
amaranth - A modern hardware definition language and toolchain based on Python