bsc VS linux-on-litex-vexriscv

Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

[1] https://github.com/ucb-bar/chipyard

[2] https://github.com/SpinalHDL/SpinalHDL

[3] https://github.com/B-Lang-org/bsc

What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?

In a previous project we used Haskell that compiled down to Verilog to design hardware. Think along the lines of BlueSpec or Clash. Haskell would force you to spell out the new state as a function of the old state of the system. This would let us do gate-level simulations of the hardware we designed. Coupled with Haskell's penchant for using primes to mean "the new value of", stuff like x' = f x was very common.

You should look at Bluespec, they are doing some interesting stuff.

And I've been involved in a project that's making heavy use of Bluespec: https://github.com/B-Lang-org/bsc/

Same problem though - you have to transpile it down to Verilog to use it in anything beyond a simulation.

FPGA Thread: Bluespec SystemVerilog is now completely open source, very nice HDL although quite opinionated.

https://github.com/B-Lang-org/bsc

it's Haskell underneath (https://xkcd.com/356/)

With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

Hello, we are planning to rebuild a computer architectures course at uni and the idea is to teach the basics using the riscv architecture. We are looking for an affordable development board that could be used to demonstrate both bare-metal programming as well as interfacing hardware via mmap from OS to build up the experience with accessing the registers directly, and then introducing virtual memory, memory hierarchy, etc. So far it seems like a best option to utilize some compatible FPGA development board and the litex ( https://github.com/litex-hub/linux-on-litex-vexriscv ) project to achieve the afforementioned. Would you have any comment on that or perhaps some other recommendation for an affordable development board? Thanks for any tips.

The repo below has support for building a 32bit RISC-V CPU for de10nano. It also includes information about booting Linux.

https://github.com/litex-hub/linux-on-litex-vexriscv

The CPU will likely have a clock speed around 100Mhz, far slower than the 1.5Ghz 64bit cores on the VisionFive 2 or Pi4. The FPGA might still be useful if you want to customize the CPU or integrate other custom hardware.

You can run linux even on an entirely open source from hardware to software toolchain: https://github.com/litex-hub/linux-on-litex-vexriscv

On the other hand, if you really want a budget FPGA board under 100 USD that can implement a Linux-capable RISC-V SoC, you will need to implement a simple 32-bit one but indeed possible. See https://github.com/litex-hub/linux-on-litex-vexriscv for instance. You will get additional frequencies (still an order of 100 MHz though), I/O ports and such if you can spend 200 to 300 USD.

An Artix 7 100k (like in the 'big' Arty A7 board) will comfortably fit 4 VexRiscv @ 100 MHz in a Litex SoC with all the bells and whistles; you can already fit a SoC with 2 Vex in the smaller 35k. Running Linux on that is very easy.

Accessibility has improved significantly over the last few years. You can now buy any of the Lattice iCE40 or ECP5 boards from this page and use the yosys open-source workflow to upload real designs to the cores, including soft cores capable of running real, unmodified Linux. These tools are actively developed and are used by the open-source FPGA community at large (with the iCE40 and ECP5 receiving massive upticks in mindshare as a result).