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1-3. I'm not familiar with SystemVerilog, only Verilog. Even with Verilog I'm not really that good in. My biggest project was a small RISC-V core, that didn't even use non-synthesizable code. I didn't even manage to use the DRAM of my DE10-Lite. I'm mostly writing this project, because the Verilog syntax is just annoying to me and I wanna have something more readable.
You should look at Bluespec, they are doing some interesting stuff.
Hi, great to see more HDLs coming, especally ones inspired by rust. I've been working on my own rust inspired HDL spade http://spade-lang.org/ https://gitlab.com/spade-lang/spade for a while so I can probably provide some insight and join the discussion:)
For spade, I have a hand written recursive descent parser which I'm very happy with and would highly recommend. I've also heard lots of people recommend https://crates.io/crates/chumsky. For us language implementors, there is a great lang-dev channel on the rust community discord https://discord.gg/rust-lang-community