Verilog Is Weird

This page summarizes the projects mentioned and recommended in the original post on news.ycombinator.com

Our great sponsors
  • InfluxDB - Build time-series-based applications quickly and at scale.
  • talent.io - Download talent.io’s Tech Salary Report
  • SonarQube - Static code analysis for 29 languages.
  • Scout APM - Truly a developer’s best friend
  • clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    Oh boy, this is a sore subject for me.

    It's pretty obvious that Verilog and VHDL, modeled after C and ADA respectively which both are imperative languages, are the entirely wrong paradigm for hardware design where circuits are combined and "everything happens in parallel". It becomes even more obvious when you've tried a functional alternative, like for example Clash (which is essentially a Haskell subset that compiles to Verilog/VHDL: https://clash-lang.org).

    The problem is, it is hard, if not downright impossible, to get the industry to change. Many will tell you, often in almost literally these words, "why would I use any language that is not the industry standard" (I honestly have heard that many times, even in instances where I said don't want to talk about it since I know how those discussions end). But even for people that are interested it might be very hard to switch to something like Clash and not give up almost immediately.

    Unlike imperative languages, functional languages with a rich modern type system like Haskell are hard to wrap your head around. It's no news to any Software Engineer that Haskell can be very hard to get into for even experienced software engineers. In 2005, after already having more than a decade of programming experience in C, C++, Java, Assembly, python (obviously not all of these for the same duration) and many other languages, I thought any new language would mostly be "picking up new syntax". But Haskell proved me very wrong on that. In was like re-learning programming, but extremely worth it and I still cherish it.

    And to my surprise, when I got heavily into FPGAs, this proved even more the case when building sequential logic, because the paradigm fits so much better. My Clash code is much smaller, but much more readable and easier to understand than Verilog/VHDL code. And it's made up of reusable components. That's mainly because functional languages allow for abstraction that Verilog/VHDL don't, and often the only recourse is very awkward "generated" code.

    So by now, I have fully switched to using Clash for my projects, and only use Verilog and VHDL for simple glue logic (where the logic is trivial and extra compilation step would be awkward) or for modifying existing logic. But try to get Hardware Engineers who probably don't have any interest in learning a functional programming language to approach such an entirely different paradigm with an open mind. I've gotten so many bogus replies that just show that the engineer has no idea what higher order functional programming with advanced type system means, and I don't blame them, but this makes discussion extremely tiring.

    So that basically leaves the intersection of people that are both enthusiastic software engineers with an affection for e.g. Haskell, and who are enthusiastic in building hardware, and it leaves me longing for the world that could exist.

  • bsc

    Bluespec Compiler (BSC) (by B-Lang-org)

  • InfluxDB

    Build time-series-based applications quickly and at scale.. InfluxDB is the Time Series Data Platform where developers build real-time applications for analytics, IoT and cloud-native services in less time with less code.

  • charbel

    Write synthesizable FPGA code with Clojure syntax

    SV and VHDL are nasty languages, but as you said, they are "industry standard". Chisel and Haskell-based approaches are better but virtually nobody adopts them.

    I tried to go in another direction, to make design code shorter by using Clojure syntax. The result is here: https://github.com/m1kal/charbel and works for simple modules. I don't expect wide adoption, but we need to look for new directions instead of sticking to the methods and languages from the 80s.

  • PipelineC

    A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

    If anyone is interested in alternatives to Verilog, check out PipelineC. Great for software folks getting into hardware, helps avoid issues like blocking vs non blocking confusion, whats a register, etc. Lots of other features too.

    https://github.com/JulianKemmerer/PipelineC/wiki

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

Suggest a related project

Related posts