Top 23 Xilinx Open-Source Projects

• openwifi

  10 3,566 7.3 C

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

  

Project mention: Hold on there: WPA3 connections fail after 11 hours | news.ycombinator.com | 2024-01-27

There is some open source firmware for very old WiFi chips:

https://wiki.debian.org/Firmware/Open#Radio

There is also some FPGA based open source WiFi chip things:

https://github.com/open-sdr/openwifi

• openFPGALoader

  13 1,044 9.2 C++

  Universal utility for programming FPGA

Project mention: STEPS to install ISE 14.7 in DEBIAN 12 | /r/FPGA | 2023-06-23

Another way to flash the devices in Linux is to use https://github.com/trabucayre/openFPGALoader which supports a variety of cables and devices. It also supports the Xilinx Virtual Cable protocol, which allows you to use Xilinx tools like ChipScope with almost any cable.

• InfluxDB

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• hdmi

  7 1,014 4.7 SystemVerilog

  Send video/audio over HDMI on an FPGA

  

Project mention: HDMI Forum Rejects Open-Source HDMI 2.1 Driver Support Sought by AMD | news.ycombinator.com | 2024-02-28

Relevant caveat from its readme: https://github.com/hdl-util/hdmi?tab=readme-ov-file#hdmi-ado...

• biriscv

  6 749 0.0 Verilog

  32-bit Superscalar RISC-V CPU

Project mention: Need help with designing a basic RISC V processor? | /r/RISCV | 2023-06-21

• vivado-risc-v

  6 738 7.5 Tcl

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

• prjxray

  8 736 8.4 Python

  Documenting the Xilinx 7-series bit-stream format.

  

Project mention: AMD Proposes an FPGA Subsystem User-Space Interface for Linux | news.ycombinator.com | 2024-01-04

• edalize

  4 593 7.2 Python

  An abstraction library for interfacing EDA tools

• SaaSHub

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• Vitis_Accel_Examples

  3 468 8.0 Makefile

  Vitis_Accel_Examples

  

• wb2axip

  51 434 3.1 Verilog

  Bus bridges and other odds and ends

• xilinx_axidma

  1 428 10.0 C

  A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

Project mention: Petalinux <---> FPGA using DMA | /r/FPGA | 2023-12-08

I recently got this kind of working, using this driver https://github.com/bperez77/xilinx_axidma. Even after using this driver I had to make changes to the auto generated device tree to get it up and running. This driver also comes with a userspace library and examples that work. I was unable to get the axidmatest.c provided by Xilinx to work.

• red-pitaya-notes

  1 316 9.0 Tcl

  Notes on the Red Pitaya Open Source Instrument

• hlslib

  1 287 3.7 C++

  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

• hdl_checker

  4 183 0.0 Python

  Repurposing existing HDL tools to help writing better code

• fpga-docker

  2 66 0.0 Makefile

  Tools for running FPGA vendor toolchains with Docker

• BrianHG-DDR3-Controller

  2 60 10.0 SystemVerilog

  DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

• neorv32-setups

  5 53 8.6 VHDL

  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Project mention: How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG? | /r/FPGA | 2023-08-03

Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.

• Alveo-PYNQ

  1 45 1.8 Jupyter Notebook

  Introductory examples for using PYNQ with Alveo

  

• PicoBlaze_Simulator_in_JS

  7 22 9.0 JavaScript

  Simulator (more accurately: an assembler and an emulator) for Xilinx PicoBlaze, runnable in a browser.

Project mention: What do the cores of good assemblers (the things that come after tokenizing, parsing, and preprocessing, the thing which actually convert mnemonics to opcodes) look like? Are they just a bunch of hard-to-follow if-branchings, or do they somehow use polymorphism to avoid that? | /r/learnprogramming | 2023-10-24

For my Bachelor thesis, I made a PicoBlaze Assembler and Emulator in JavaScript. I've discussed it on many Internet forums, and quite a few people have complained that the core of my assembler is hard-to-follow due to lots of if-branchings. So, what is the other way of making the core of the assembler?

• nix-fpga-tools

  2 20 2.6 Nix

• kvm-ip-zynq

  2 19 0.0 VHDL

  KVM over IP Gateway targeting Zynq-7000 SoC

• ise14

  2 15 10.0 PowerShell

  EDA Tools: Xilinx ISE 14.7 Dockerfile

Project mention: STEPS to install ISE 14.7 in DEBIAN 12 | /r/FPGA | 2023-06-23

I never had problems running ISE 14.7 on Debian based platforms. What I do to use Platform Cable, is to put the firmware files in /usr/share and the following rules in /etc/udev/rules.d/ https://github.com/vmunoz82/ise14/blob/main/xusbdfwu.rules

• SoC

  1 11 1.1 VHDL

  Github Repo for Embedded FPGA course by Vincent Claes

• wbicapetwo

  2 8 0.0 Verilog

  Wishbone to ICAPE interface conversion

• SaaSHub

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Xilinx related posts

• AMD Proposes an FPGA Subsystem User-Space Interface for Linux

  3 projects | news.ycombinator.com | 4 Jan 2024

• What do the cores of good assemblers (the things that come after tokenizing, parsing, and preprocessing, the thing which actually convert mnemonics to opcodes) look like? Are they just a bunch of hard-to-follow if-branchings, or do they somehow use polymorphism to avoid that?

  1 project | /r/learnprogramming | 24 Oct 2023

• How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?

  1 project | /r/FPGA | 3 Aug 2023

• STEPS to install ISE 14.7 in DEBIAN 12

  2 projects | /r/FPGA | 23 Jun 2023

• Learn Vanilla JS before React, CSS before Tailwind?

  1 project | /r/webdev | 9 Apr 2023

• Dropping EDA-GUI's 101

  1 project | /r/FPGA | 17 Feb 2023

• Can you help me dataflow checking failure on vitis hls?

  1 project | /r/FPGA | 12 Feb 2023
• A note from our sponsor - SaaSHub
  www.saashub.com | 5 May 2024

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