Top 19 soc Open-Source Projects

• VexRiscv

  21 2,259 7.3 Assembly

  A FPGA friendly 32 bit RISC-V CPU implementation

  

Project mention: Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide | /r/RISCV | 2023-10-23

With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

• PacketStreamer

  15 1,852 2.8 Go

  :star: :star: :star: Distributed tcpdump for cloud native environments :star: :star: :star:

  

Project mention: Traffic Mirroring in Azure | /r/AskNetsec | 2023-05-13

Also: - https://github.com/deepfence/PacketStreamer

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• chipyard

  5 1,432 9.7 Scala

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  

Project mention: Chisel: A Modern Hardware Design Language | news.ycombinator.com | 2023-12-27

It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

[0]: https://github.com/ucb-bar/chipyard

[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

• neorv32

  77 1,429 9.9 C

  :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24

• Sooty

  1 1,283 0.0 Python

  The SOC Analysts all-in-one CLI tool to automate and speed up workflow.

• xboot

  2 783 8.4 C

  The extensible bootloader for embedded system with application engine, write once, run everywhere.

  

• tenzir

  15 612 10.0 C++

  Open source security data pipelines.

  

Project mention: Vector: A high-performance observability data pipeline | news.ycombinator.com | 2024-03-17

We're building something similar at Tenzir, but more for operational security workloads. https://docs.tenzir.com

Differences to Vector:

- An agent has optional indexed storage, so you can store your data there and pick it up later. The storage is based on Apache Feather, Parquet's little brother.

- Pipelines operators both work with data frames (Arrow record batches) or chunks of bytes.

- Structured pipelines are multi-schema, i.e., a single pipeline can process streams of record batches with different schemas.

• SaaSHub

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• riscv_vhdl

  2 581 8.8 Verilog

  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

• SIEM

  1 513 6.3

  SIEM Tactics, Techiques, and Procedures

• Vitis_Accel_Examples

  3 468 8.0 Makefile

  Vitis_Accel_Examples

  

• ThreatHunting-Keywords

  1 338 9.4 HTML

  Awesome list of keywords and artifacts for Threat Hunting sessions

Project mention: List of offensive tools keywords for ThreatHunting | /r/cybersecurity | 2023-05-18

more information here: https://github.com/mthcht/ThreatHunting-Keywords

• rggen

  3 280 7.7 Ruby

  Code generation tool for control and status registers

  

• awesome-lists

  1 204 9.8 PowerShell

  Security lists for SOC detections (by mthcht)

Project mention: List of suspicious ports | /r/cybersecurity | 2023-05-22

• SaxonSoc

  1 141 5.0 Scala

  SoC based on VexRiscv and ICE40 UP5K

  

• Purpleteam

  1 122 7.8 PowerShell

  Purpleteam scripts simulation & Detection - trigger events for SOC detections

• Introduction-to-SoC-Design-Education-Kit

  1 78 4.8 HTML

  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals

  

• neorv32-setups

  5 53 8.6 VHDL

  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Project mention: How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG? | /r/FPGA | 2023-08-03

Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.

• slides-talks

  1 36 5.1

  My own cybersecurity research talks/slides

Project mention: Dumping Firmware for fun and learning [pdf] | news.ycombinator.com | 2024-01-20

• petalinux_notes

  1 2 5.7 SystemVerilog

  Notes after working with Zynq platform using vivado and petalinux

Project mention: Need a teacher for Zynq SoC | /r/FPGA | 2023-12-07

Got some notes of the basic flow for Xilinx SOC chips. Check this out https://github.com/2uger/petalinux_notes. Past year i was working with Zynq-7000, got a lot of troubles and figure them out. Nothing unique, but create my custom design, use DMA, write linux drivers and so on. I like talk about this stuff without money, if you really interested, peace.

• SaaSHub

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• Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide

  4 projects | /r/RISCV | 23 Oct 2023

• An example of how to add the A ISA extension's LR/SC operations into an open-source architecture

  1 project | /r/RISCV | 24 Jul 2023

• RISC-V with AXI Peripheral

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• Intel discontinues Nios II IP

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• NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL

  1 project | /r/VHDL | 18 May 2023

• NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL

  1 project | /r/opensource | 18 May 2023

• NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL

  1 project | /r/FPGA | 18 May 2023
• A note from our sponsor - SaaSHub
  www.saashub.com | 4 May 2024

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