Top 6 C++ Modeling Projects

blender

37 11,453 10.0 C++

Official mirror of Blender

Project mention: I fully support this. | /r/KerbalSpaceProgram | 2023-06-24

Please try looking through some large open source projects and contributing major contributions by familiarizing yourself with the code base, learning multiple programming languages, and not having major bugs in your code. I'd imagine you wouldn't want to do this.

CHRONO

7 2,040 9.9 C++

High-performance C++ library for multiphysics and multibody dynamics simulations (by projectchrono)

Project mention: Any Good Alternatives for Matlab? | /r/AskEngineers | 2023-06-16

Hopsan https://liu.se/en/research/hopsan and Project Chrono https://projectchrono.org/ may be good Simulink alternatives.

InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
gem5

3 1,412 9.8 C++

The official repository for the gem5 computer-system architecture simulator.

Project mention: Hot Chips 2023: Arm’s Neoverse V2 | news.ycombinator.com | 2023-09-12

The idea is to write a C++ model that that produces cycle accurate outputs of the branch predictor, core pipeline, queues, memory latency, cache hierarchy, prefetch behaviour, etc. Transistor level accuracy isn't needed as long as the resulting cycle timings are identical or near identical. The improvement in workload runtime compared to a Verilog simulation is precisely because they aren't trying to model every transistor, but just the important parameters which effect performance.
Let's take a simple example: Instead of modeling a 64-bit adder in all its gory transistor level detail, you can just have the model return the correct data after 1 "cycle" or whatever your ALU latency is. As long as that cycle latency is the same as the real hardware, you'll get an accurate performance number.
What's particularly useful about these models is they enable much easier and faster state space exploration to see how a circuit would perform, well before going ahead with the Verilog implementation, which relatively speaking can take circuit designers ages. "How much faster would my CPU be if it had a 20% larger register file" can be answered in a day or two before getting a circuit designer to go try and implement such a thing.
If you want an open source example, take a look at the gem5 project (https://www.gem5.org). It's not quite as sophisticated as the proprietary models used in industry, but it's a used widely in academia and open source hardware design and is a great place to start.

riscv-perf-model

1 98 7.9 C++

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
AobaAPI

2 34 0.0 C++

C++ API/library for 3D polygonal mesh modeling
ToolboxR

2 5 8.6 C++

Discrete Time C++ Modeling Library

Project mention: New in ToolboxR Control Library (Trajectory Generation) | news.ycombinator.com | 2023-11-24

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).