riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model (by riscv-software-src)
Add to my DEV experience Modeling out-of-order Performance analysis risc-v
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riscv-perf-model reviews and mentions

Posts with mentions or reviews of riscv-perf-model. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-02.
  • Do Necessary Tools Exist for RISC-V Verification?
    2 projects | news.ycombinator.com | 2 Apr 2023
    I 100% agree on verilator. It’s by far the most efficient tool for many simulation and verification needs. Hands down. Even more so if you are building CPUs

    UVM definitely has its place still in verification flows. It for something as complex and flexible as a CPU for sure, it’s hard to beat the amount of cycles and coverage you get from verilator. (EDA license fees are a big part of that, but also the fact that verilator generates just C++ code you can integrate with the rest of your s/w flow is invaluable).

    But: What is also important for CPU is good validation and compliance test, (random or replayed or directed) instruction stream generators, ISS to validate agains etc. There are so much more scenarios to check because a CPU needs to handle any sequence of any instructions flawlessly.

    Those tools are also crucial. And they are being built or sold for RISC-V now too. And also: I much prefer combining those with verilator than with commercial eda tools. And don’t forget: before you start building a lot of RTL, you’ll typically will also build C based higher level performance models of the micro architecture, eg https://github.com/riscv-software-src/riscv-perf-model

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7.9
12 days ago

riscv-software-src/riscv-perf-model is an open source project licensed under Apache License 2.0 which is an OSI approved license.

The primary programming language of riscv-perf-model is C++.

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