wbuart32 | Examples | |
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4 | 3 | |
254 | 55 | |
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4.6 | 4.4 | |
3 months ago | 8 months ago | |
Verilog | Verilog | |
GNU General Public License v3.0 only | MIT License |
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wbuart32
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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CDC interview question clarification
Try this one.
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AXI Stream basics for beginners, Here's a video I made because a bunch of people suggested I do something AXI!
For example, some time after I built my own first serial port transmitter and receiver, someone tried using them in composition: A host (i.e. PC) would transmit a bunch of data, get received by the FPGA, processed by the receiver, and then the data would be sent back to the host via the transmitter. This is a hard test to get right, and my own design failed at the task. (It only returned every other byte!) What I learned from this is that the transmitter must take exactly (10*BAUD_CLOCKS) to transmit a byte. That also means that READY must be high on the last clock cycle of the byte to avoid falling behind. Let's just say that my own serial port wasn't (initially) up to the task. Among other things, the serial port receivers output "VALID" was only one cycle long, and didn't get latched anywhere if the transmitter wasn't ready for it. As I recall, we spent many days scratching our heads at the problem. Eventually, the person using my FPGA switched his host to sending 2-stop bits and things started working. Later, and only a long time later, did I ever find the off-by-one bug in the STOP bit state. My point? Serial port composition is an exacting test, and therefore a good one to work with. You ought to try it.
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How can I get Verilator to Prompt for User Input?
The core component to the single simulated to TCP port can be found here, in uartsim.cpp. You can find a companion software program that will forward the same TCP port to a hardware serial port here, under the name netuart.cpp.
Examples
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Vivado Ethernet IP
I made a video that shows how to do this on your own (github link to code), or vivado has the Axi Ethernet Lite core, it's one of the only MAC cores that has a licence included with vivado. I haven't used it recently, though, so I can't speak for its ease of use.
- I'm confused about creating RTL code vs "regular coding" style in Verilog.
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AXI Stream basics for beginners, Here's a video I made because a bunch of people suggested I do something AXI!
Looking over your serial port design, it looks you are struggling to get your UART to work. Has it seen hardware?
What are some alternatives?
zipcpu - A small, light weight, RISC CPU soft core
ZCU102-Ethernet - Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
wbicapetwo - Wishbone to ICAPE interface conversion
Verilog_Calculator_Matrix_Multiplication - This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
biriscv - 32-bit Superscalar RISC-V CPU
openarty - An Open Source configuration of the Arty platform
FakePGA - Simulating Verilog designs on a microcontroller
dpll - A collection of phase locked loop (PLL) related projects
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
wbscope - A wishbone controlled scope for FPGA's
videozip - A ZipCPU SoC for the Nexys Video board supporting video functionality
interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing