verilog-ethernet VS pyxsi

Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.

For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.

For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.

No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.

So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.

I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.

I was studying Alex Forencich's FCS verilog and noticed the following always block:

This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet

These three environments are glued together using pyxsi, which embeds Xilinx's simulator kernel (xsim). The result is a complicated monolith, but avoids the following "Bad Practices for Complex Dataflow":

Adam mentions it in his Aduvio post, but pyxsi shows how to stack Python on C/C++ on Vivado. (Disclaimer: mine.)

The sketch here is a little stale but shows the general idea.

I'm trying to understand if we can use the Vivado XSI to make our verification tasks easier and improve our coverage via a more productive language like C++ or python. I found an interesting project (https://github.com/gsmecher/pyxsi) that uses it but I'm still unsure if this is worth investing time on (given how many issues Xilinx tools usually have).