verible VS Surelog

verible

• How to instance module with auto-completion for verilog in neovim?
  1 project | /r/neovim | 25 Aug 2023

  I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?

• Verilog LRM syntax rules
  1 project | /r/Compilers | 24 Mar 2022

  BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.

• Reliable Verilog dependency analysis
  3 projects | /r/FPGA | 5 Feb 2022

  You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.

• svls VS verible - a user suggested alternative
  2 projects | 3 Nov 2021
• Tools like Scitools Understand but support Verilog
  4 projects | /r/FPGA | 19 Sep 2021

  https://github.com/chipsalliance/verible (may not do actual syntax checking)

• Forking rustfmt for another language
  1 project | /r/rust | 19 Feb 2021

  You might be interested in this though.

Surelog

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Tracking mentions began in Dec 2020.