tang-doc
neorv32-setups
| tang-doc | neorv32-setups | |
|---|---|---|
| 1 | 5 | |
| 3 | 52 | |
| - | - | |
| 0.0 | 8.6 | |
| over 2 years ago | 7 days ago | |
| HTML | VHDL | |
| MIT License | BSD 3-clause "New" or "Revised" License |
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tang-doc
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Micro usb not being detected
From This pinout, can I use an external microcontroller that is connected to the pins of the board to program the FPGA?
neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
What are some alternatives?
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
platform-gd32v - GD32V: development platform for PlatformIO
litex - Build your hardware, easily!
PlatformIO - Your Gateway to Embedded Software Development Excellence :alien:
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpu - IEEE 754 floating point library in system-verilog and vhdl
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
ORCA-risc-v - RISC-V by VectorBlox
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation