spi-fpga
sdram-fpga
spi-fpga | sdram-fpga | |
---|---|---|
2 | 2 | |
157 | 105 | |
- | - | |
0.0 | 10.0 | |
about 3 years ago | over 2 years ago | |
VHDL | VHDL | |
MIT License | MIT License |
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spi-fpga
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The accelerometer on the CYC1000 FPGA board.
Last year I did experiments with the accelerometer on the CYC1000 FPGA board. The result is the Spirit Level example for my Git repository with SPI controllers. I also started using GHDL in GitHub Actions to automate my simulations. It is an easy-to-use CI for VHDL projects. https://github.com/jakubcabal/spi-fpga
- Does anyone have a Slave Quad SPI in VHDL?
sdram-fpga
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Seeking Help with SDRAM Controller Debugging
Initially, I attempted to adapt an SDRAM [controller project I found on GitHub]( https://github.com/nullobject/sdram-fpga/blob/master/sdram.vhd) to my board by configuring the necessary parameters such as timing constants and memory dimensions.
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SDRAM clock vs controller clock vs system clock
here you go
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
uart-for-fpga - Simple UART controller for FPGA written in VHDL
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
w11 - PDP-11/70 CPU core and SoC
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).