sdram-fpga
wb_spi_bridge
| sdram-fpga | wb_spi_bridge | |
|---|---|---|
| 2 | 2 | |
| 105 | 19 | |
| - | - | |
| 10.0 | 0.0 | |
| over 2 years ago | over 2 years ago | |
| VHDL | VHDL | |
| MIT License | BSD 3-clause "New" or "Revised" License |
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sdram-fpga
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Seeking Help with SDRAM Controller Debugging
Initially, I attempted to adapt an SDRAM [controller project I found on GitHub]( https://github.com/nullobject/sdram-fpga/blob/master/sdram.vhd) to my board by configuring the necessary parameters such as timing constants and memory dimensions.
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SDRAM clock vs controller clock vs system clock
here you go
wb_spi_bridge
What are some alternatives?
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
uart-for-fpga - Simple UART controller for FPGA written in VHDL
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.