satcat5
FPGA_RealTime_and_Static_Sobel_Edge_Detection
| satcat5 | FPGA_RealTime_and_Static_Sobel_Edge_Detection | |
|---|---|---|
| 25 | 3 | |
| 390 | 36 | |
| 10.5% | - | |
| 3.8 | 0.0 | |
| 2 months ago | over 2 years ago | |
| VHDL | Verilog | |
| CERN Open Hardware Licence Version 2 - Weakly Reciprocal | MIT License |
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satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
FPGA_RealTime_and_Static_Sobel_Edge_Detection
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Sobel edge detection
Hi, you might be interested on having a look at this project. The main RTL for the convolution is in sobel_convolution.v
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
I posted this project on this sub three weeks ago,
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Real-Time Sobel Edge Detection using FPGA (repo link in the comments)
Project repository
What are some alternatives?
verilog-ethernet - Verilog Ethernet components for FPGA implementation
litex - Build your hardware, easily!
SpinalHDL - Scala based HDL
surf - A huge VHDL library for FPGA development
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
FPGA_OV7670_Camera_Interface - Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
opentitan - OpenTitan: Open source silicon root of trust
chisel - Chisel: A Modern Hardware Design Language
ULX3S_FPGA_Camera_Streaming - Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board