riscv-tests
RISCV-FiveStage
| riscv-tests | RISCV-FiveStage | |
|---|---|---|
| 9 | 4 | |
| 783 | 89 | |
| 2.3% | - | |
| 7.5 | 0.0 | |
| 1 day ago | over 3 years ago | |
| C | Scala | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-tests
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Computerraria: A fully compliant RISC-V computer inside Terraria
Fully compliant to RISC-V how? Is it conforming to a specific RVI profile? The project states "By emulating a complete rv32i instruction set inside the wiring system of Terraria, we push back speeds to the early 70s era, tossing the ball firmly back into the court of silicon engineer without losing any software functionality."
So this is building a RISC-V *microcontroller* but what version of the ISA? 2.2 from 2017? Is it sucessfully passing conformance tests (https://github.com/riscv-software-src/riscv-tests)? I don't want to dunk on the project, but the title is over-selling and not scoping the context of the work. I look forward to some more updates from @misprit7!
Note: I'm the working group lead for distro-integration within the RISC-V Software Ecosystem (RISE) group.
- Verification
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
- Efficient Way To Generate Test Benches For MIPS Processor?
- We need some support
- Available (official) test suite?
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
- Compliance tests official repository
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Tips on building a RISC-V processor on FPGA
Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.
RISCV-FiveStage
- Tips on building a RISC-V processor on FPGA
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Planning to develop a CPU on an FPGA. How can I program it?
I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage
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Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer
It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc.
https://github.com/PeterAaser/RISCV-FiveStage
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Want to get started.What to buy?
If you want to do something big but simulated you can try to do this coursework https://github.com/PeterAaser/RISCV-FiveStage I made for my university, teaching CPU design. It's in chisel though, which is different from verilog. Be sure to look at the intro first.
What are some alternatives?
riscv-arch-test
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation
cortex-m0-soft-microcontroller - Soft-microcontroller implementation of an ARM Cortex-M0
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
litex - Build your hardware, easily!
nmigen-tutorial - A tutorial for using nmigen
riscof
tdt4255-chisel-intro
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
wyre - Hardware definition language that compiles to Verilog