RISCV-FiveStage VS cortex-m0-soft-microcontroller

I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage

It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc.

https://github.com/PeterAaser/RISCV-FiveStage

If you want to do something big but simulated you can try to do this coursework https://github.com/PeterAaser/RISCV-FiveStage I made for my university, teaching CPU design. It's in chisel though, which is different from verilog. Be sure to look at the intro first.

I did a similar project to implement a soft-microcontroller based on an ARM Cortex-M0. My strategy was to compile the code, convert the binary into ASCII and use it to initialize the value of a general purpose RAM block during HDL synthesis. In case you want to take a look: https://github.com/vfinotti/cortex-m0-soft-microcontroller. The downside is that changing the program implies in running the synthesis again.