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[1]: https://github.com/greatscottgadgets/luna/blob/master/exampl...
Migen, the Python-based project nMigen is based off, has been around for longer and has some large projects, such as LiteX[2] which uses Migen to glue together entire SoCs, including peripheral cores such as GigE, DDR3/4, SATA, PCIe, etc, all written in Migen, and is pretty widely used. It also pulls in Verilog/VHDL designs (such as many of its CPU core choices) since it's easy to pull in those from the Python side.
[2]: https://github.com/enjoy-digital/litex/
It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc.
https://github.com/PeterAaser/RISCV-FiveStage
Shameless plug: I had a similar impression when looking at nMigen, so I wrote a new HDL called Wyre [0]. No metaprogramming, but a Verilog-like language with a focus on ergonomics instead. I'm currently making a basic Minecraft clone for the Lattice iCE40 with it.
[0] https://github.com/nickmqb/wyre
I've had this recommended and it looks v promising! https://vivonomicon.com/2020/04/14/learning-fpga-design-with...
Someone above has mentioned Robert Baruch too: https://github.com/RobertBaruch/nmigen-tutorial
I also found this helpful: http://blog.lambdaconcept.com/doku.php?id=nmigen:tutorial
And there is of course the IRC channel if you want to ask people questions, #nmigen on irc.freenode.net