Planning to develop a CPU on an FPGA. How can I program it?

• tdt4255-chisel-intro

  1 22 0.0 Scala

I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage

• RISCV-FiveStage

  4 89 0.0 Scala

  Marginally better than redstone

I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• cortex-m0-soft-microcontroller

  1 19 0.0 SystemVerilog

  Soft-microcontroller implementation of an ARM Cortex-M0

I did a similar project to implement a soft-microcontroller based on an ARM Cortex-M0. My strategy was to compile the code, convert the binary into ASCII and use it to initialize the value of a general purpose RAM block during HDL synthesis. In case you want to take a look: https://github.com/vfinotti/cortex-m0-soft-microcontroller. The downside is that changing the program implies in running the synthesis again.

• 4-bit-CPU-Compiler

  1 0 1.8 Python

  Python script to take in Pseudo assembly code and translate it into Verilog for case statements in a ROM module.

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