RISCV-FiveStage VS nmigen-tutorial

I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage

It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc.

https://github.com/PeterAaser/RISCV-FiveStage

If you want to do something big but simulated you can try to do this coursework https://github.com/PeterAaser/RISCV-FiveStage I made for my university, teaching CPU design. It's in chisel though, which is different from verilog. Be sure to look at the intro first.

nmigen-tutorial

I've had this recommended and it looks v promising! https://vivonomicon.com/2020/04/14/learning-fpga-design-with...

Someone above has mentioned Robert Baruch too: https://github.com/RobertBaruch/nmigen-tutorial

I also found this helpful: http://blog.lambdaconcept.com/doku.php?id=nmigen:tutorial

And there is of course the IRC channel if you want to ask people questions, #nmigen on irc.freenode.net

If you are already familiar with Python I could recommend start with this tutorial: https://github.com/RobertBaruch/nmigen-tutorial