rggen
vscode-terosHDL
rggen | vscode-terosHDL | |
---|---|---|
3 | 3 | |
279 | 495 | |
1.8% | 3.2% | |
7.7 | 9.2 | |
3 months ago | 6 days ago | |
Ruby | JavaScript | |
MIT License | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rggen
-
RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
-
RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
-
RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
vscode-terosHDL
-
Sigasi's price
You can try TerosHDL: https://terostechnology.github.io/terosHDLdoc/
- (System)Verilog Linting in VSCode?
-
sublime System Verilog vs TerosHDL VS Code vs Synopsys Euclide
Please, open an issue in: https://github.com/TerosTechnology/vscode-terosHDL
What are some alternatives?
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
hdl_checker - Repurposing existing HDL tools to help writing better code
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
PeakRDL-ipxact - Import and export IP-XACT XML register models
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
edalize - An abstraction library for interfacing EDA tools
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler