rggen-verilog-rtl VS rggen

Compare rggen-verilog-rtl vs rggen and see what are their differences.

rggen-verilog-rtl

Common Verilog RTL modules for RgGen (by rggen)
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rggen

Code generation tool for control and status registers (by rggen)
Verilog Systemverilog Uvm Rtl Ral Csr soc Fpga Asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda Vhdl wishbone-bus
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rggen-verilog-rtl rggen
1 3
5 280
- 2.1%
4.4 7.7
4 months ago 3 months ago
Verilog Ruby
MIT License MIT License
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rggen-verilog-rtl

Posts with mentions or reviews of rggen-verilog-rtl. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-25.

rggen

Posts with mentions or reviews of rggen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-13.
  • RgGen v0.28.0
    1 project | /r/u_taichi730 | 11 Oct 2022
    I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
  • RgGen update (support C header file generation)
    3 projects | /r/u_taichi730 | 13 Jun 2022
    RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
  • RgGen update
    4 projects | /r/FPGA | 25 Mar 2022
    I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0

What are some alternatives?

When comparing rggen-verilog-rtl and rggen you can also consider the following projects:

rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen

PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input

rggen-vhdl-rtl

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

PeakRDL-ipxact - Import and export IP-XACT XML register models

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

edalize - An abstraction library for interfacing EDA tools

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

veryl - Veryl: A Modern Hardware Description Language

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

systemrdl-compiler - SystemRDL 2.0 language compiler front-end

rggen-verilog-rtl vs rggen-sv-rtl rggen vs PeakRDL-uvm rggen-verilog-rtl vs rggen-vhdl-rtl rggen vs open-register-design-tool rggen vs PeakRDL-ipxact rggen vs vscode-terosHDL rggen vs edalize rggen vs rggen-sv-rtl rggen vs hdlConvertor rggen vs veryl rggen vs gf180mcu-pdk rggen vs systemrdl-compiler