rggen VS systemrdl-compiler

Compare rggen vs systemrdl-compiler and see what are their differences.

rggen

Code generation tool for control and status registers (by rggen)
Verilog Systemverilog Uvm Rtl Ral Csr soc Fpga Asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda Vhdl wishbone-bus
Source Code
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systemrdl-compiler

SystemRDL 2.0 language compiler front-end (by SystemRDL)
systemrdl-compiler hardware-description-language Asic Fpga registers register-descriptions eda design-automation register-description-language systemrdl Csr
Source Code
systemrdl-compiler.readthedocs.io
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rggen systemrdl-compiler
3 1
279 222
1.8% 0.9%
7.7 7.3
3 months ago about 1 month ago
Ruby Python
MIT License MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

rggen

Posts with mentions or reviews of rggen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-13.
  • RgGen v0.28.0
    1 project | /r/u_taichi730 | 11 Oct 2022
    I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
  • RgGen update (support C header file generation)
    3 projects | /r/u_taichi730 | 13 Jun 2022
    RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
  • RgGen update
    4 projects | /r/FPGA | 25 Mar 2022
    I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0

systemrdl-compiler

Posts with mentions or reviews of systemrdl-compiler. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-11.

What are some alternatives?

When comparing rggen and systemrdl-compiler you can also consider the following projects:

PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input

PeakRDL-ipxact - Import and export IP-XACT XML register models

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

PeakRDL-halcpp - C++ 17 Hardware abstraction layer generator from systemrdl

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

edalize - An abstraction library for interfacing EDA tools

wavedrom - :ocean: Digital timing diagram rendering engine

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

joes-sandbox

rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen

mrisc32 - MRSIC32 ISA documentation and development

rggen vs PeakRDL-uvm systemrdl-compiler vs PeakRDL-ipxact rggen vs open-register-design-tool systemrdl-compiler vs PeakRDL-halcpp rggen vs PeakRDL-ipxact systemrdl-compiler vs PeakRDL-html rggen vs edalize systemrdl-compiler vs wavedrom rggen vs vscode-terosHDL systemrdl-compiler vs joes-sandbox rggen vs rggen-sv-rtl systemrdl-compiler vs mrisc32