Tool to generate table of memory-mapped register?

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA
SVG Cpu systemrdl-compiler Diagram Risc

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  • mrisc32

    Discontinued MRSIC32 ISA documentation and development

    • I use it extensively in my MRISC32 ISA manual (much of which is generated by a Python script): https://github.com/mrisc32/mrisc32

  • wavedrom

    :ocean: Digital timing diagram rendering engine

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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  • systemrdl-compiler

    SystemRDL 2.0 language compiler front-end

    • Also I would recommend SystemRDL for creating a definition usable in code generators: https://github.com/SystemRDL/systemrdl-compiler

  • joes-sandbox

  • PeakRDL-pdf

    Converts the SystemRDL data into pdf Register specification

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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